Books

  1. M. Coppola, M.D. Grammatikakis, R. Locatelli, G. Maruccia, L. Pieralisi, “Design of Cost-efficient Interconnect Processing Units: Spidergon STNoC”, CRC press, September 2008, ISBN: 978-1-4200-4471-3, 288 pages. Book foreword written by Prof. William J. Dally, Chairman of Computer Science, Stanford University.
  2. M.D. Grammatikakis, D. F. Hsu and M. Kraetzl, “Parallel System Interconnections and Communications”, CRC press, December 2000, ISBN: 0-849-33153-6, 412 pages. Received “Editor’s choice award” in IEEE Network column “New Books and Multimedia”, July 2001.

Edited Books

  1. G. Kornaros (Editor) Multi-Core Embedded Systems, CRC Press/Taylor & Francis Group, 2010, ISBN: 978-1-4398-1161-0, 501 pages.
  2. M.D. Grammatikakis, G. Kornaros, and N. Papadakis (Eds.), Proc. 8th Workshop on Intelligent Solutions in Embedded Systems (WISES2010), Heraklion, Greece, 2010. IEEE Catalog No: CFP10848-PRT/ART.

Chapters in Edited Books

  1. M.D. Grammatikakis, G. Kornaros and M. Coppola, “Power-Aware Multicore SoC and NoC Design “, (invited chapter), in Multiprocessor System-on-Chip: Current Trends and Future, Eds. M. Huebner, Chapter 3, Springer Verlag, 30 pages, 2010.
  2. G. Kornaros, “Application Specific Customizable Embedded Systems”, Book Chapter 2, 39 pages, in “Multi-Core Embedded Systems”, Eds. G.Kornaros, CRC Press/Taylor & Francis Group, Apr. 2010, ISBN: 978-1-4398-1161-0.
  3. G. Kornaros, D.Pnevmatikatos, and Y.Papaefstathiou, “Monitoring Services for Networks-on-Chip”, Book Chapter 8, 32 pages, in “Networks-on-Chips: Theory and Practice” Eds: Fayez Gebali, Haytham Elmiligi, and M. Watheq El-Kharashi, CRC Press, ISBN: 9781420079784, ISBN 10: 1420079786, March 25, 2009, 389 pages.
  4. L. Bononi, N. Concer and M. Grammatikakis, “System-Level Tools for NoC-based multicore design” in Embedded Multicore Architectures. Ed. G. Kornaros, Chapter 6, CRC Press, Taylor and Francis Group, 40 pages, 2009.
  5. M. Coppola, M.D. Grammatikakis, T. Basset, C. Grassman, P. Kajfasz, “IP reuse”, (invited chapter), The Medea+ Design Automation Roadmap, Eds. J. Borel, Chapter 9, 18 pages, (initially) 2005, ISBN: 2-9520704-2-3. Updated in 2008, as Chapter 7, 40 pages. Author list: M. Coppola, M.D. Grammatikakis, S. Baynes, C. Spitale, P. Bricaud and S. Sonntag.
  6. M. Coppola and M.D. Grammatikakis, “Cycle-accurate system-level modeling and performance evaluation”, (invited chapter), in Electronic Design Automation for Integrated Circuits Handbook, Eds. G. Martin, L. Lavagno and L. Scheffer, Chapter 11, Taylor and Francis Group, CRC Press, 34 pages, 2005, ISBN: 0-8493-3096-3.
  7. M. Coppola, M.D. Grammatikakis, R. Locatelli, G. Marrucia and L. Pieralisi, “Spidergon: a NoC modeling paradigm”, (invited chapter), in Model Driven Engineering for Distributed, Real-Time, and Embedded Systems, Eds. S. Gerard, J.-P. Babau, and J. Champeau, Hermes Publisher, Chapter 13, 19 pages, 2005, ISBN: 9781905209323.
  8. M.D. Grammatikakis, M. Coppola and F. Sensini, “Software for multiprocessor networks on chip”, (invited chapter), Networks on Chip, Eds. A. Jantsch and H. Tenhunen, Kluwer Academic Publisher, 24 pages, 2003, ISBN: 1-4020-7392-5. This book has made record sales for Kluwer, outselling the recent SystemC book.
  9. M.D. Grammatikakis, M. Kraetzl and E. Fleury, “Shortest-path and hot-potato routing on unbuffered toroidal networks”, (invited chapter), Defense Applications of Signal Processing, Eds. W. Moran, D. Cochran and L. B. White, Elsevier (North Holland), 2001, ISBN: 0-444-50864-3.

International Journals

  1. George Kornaros, «A soft multi-core architecture for edge detection and data analysis of microarray images», J. Syst. Architect., Volume 56, Issue 1, January 2010, Pages 48-62.
  2. G. Kornaros, A. Demiris and S. Blionas, «Lab-on-Chip for Pharmacogenomics: An Embedded System Organization Micro and Nanosystems», Volume 1, Number 1, pp. 30-40, ISSN: 1876-4029 (Print), ISSN: 1876-4037 (Online), March 2009.
  3. George Kornaros, Matthias Sund,Wolfram Lautenschlaeger, Helen-Catherine Leligou, and Theofanis Orphanoudakis, «Efficient Implementation Of A Frame Aggregation Unit For Optical Frame-Based Switching», AEÜ – International Journal of Electronics and Communications, ISSN: 1434-8411, accepted 19 September 2008, available online 5 December 2008, vol. 64, no. 1, 2010, pp 17-28.
  4. G. Kornaros and S. Blionas, «Microarchitecture of a MultiCore SoC for Data Analysis of a Lab-on-Chip Microarray», EURASIP Journal on Advances in Signal Processing, vol. 2008, Article ID 520641, 11 pages, 2008. doi:10.1155/2008/520641.
  5. J. D. Angelopoulos,, K. Kanonakis, H. C. Leligou, Th. Orphanoudakis, G. Kornaros, «Multiplexing Qos-Differentiated Traffic In An Ethernet-Based Access Network», The Mediterranean Journal of Computers and Networks, Vol. 4, No. 2, 2008.
  6. M. D. Grammatikakis, K. Papadimitriou, P. Petrakis, et al., “Security in MPSoCs: A NoC firewall and an evaluation framework”. IEEE Trans. on CAD of Integrated Circuits and Systems 34(8), 2015, pp. 1344–1357.
  7. Nikologiannis, G. Kornaros, I. Papaefstathiou, C. Kachris , «An FPGA-based Queue Management System for High Speed Networking Devices», Elsevier Journal: Microprocessors and Microsystems, Volume 28, Issues 5-6, Pages 193-350, (2 August 2004) Special Issue on FPGAs: Applications and Designs, pages 223-236, http://www.elsevier.com/locate/micpro.
  8. Ch. Kachris, Th. Orphanoudakis, I. Papaefstathiou, G. Kornaros, A. Nikologiannis, N. Zervos, «Performance Evaluation of Queue Management Implementations in Network Processing Units», WSEAS Transactions on Communications, Issue 1, Volume 4, July 2004, ISSN 1109-2742.
  9. Y. Papaefstathiou, S. Perissakis, D. Pnevmatikatos, G. Kornaros, F. Orphanoudakis, N. Nikolaou, K. Pramataris, K. Vlachos, G. Konstantoulakis, N. Zervos, «PRO3: A Hybrid NPU Architecture», IEEE Micro, vol.24, No.5, pp 20-33,http://doi.ieeecomputersociety.org/10.1109/MM.2004.55, year 2004.
  10. M.D. Grammatikakis and S. Liesche, «Priority queues and sorting methods for parallel simulation», IEEE Trans. Software Engin. – Special Section on Arch. Independent Lang. and Software Tools for Parallel Proc., SE-26 (5) , pp. 401—422, 2000.
  11. Georgios Kornaros, Dionisios Pnevmatikatos, Panagiota Vatsolaki, Georgios Kalokerinos, Chara Xanthaki, Dimitrios Mavroidis, Dimitrios Serpanos, Manolis Katevenis, «ATLAS I: Implementing a single-chip ATM switch with backpressure», IEEE Micro, 19(1), January/February 1999.
  12. M.D. Grammatikakis, D. F. Hsu, M. Kraetzl and J. Sibeyn, «Packet routing in fixed-connection networks: a survey», J. Parallel Distrib. Comput., Academic Press, 54 , pp. 77—132, 1998,.
  13. M.D. Grammatikakis, M. Kraetzl and E. Fleury, «Continuous routing in packet switches (STC104 – Telegraphos)», J. Foundations Comput. Sci. – Special Issue on Interconnection Networks, World Scientific Publishing, 9 (2) , pp. 121—138, 1998.
  14. F. K. Hwang, Y. C. Yao, and M.D. Grammatikakis, «D-move local permutation routing for the d-cube», Discrete Appl. Math., Elsevier (North Holland), 72 (3) , pp. 199—207, 1997.
  15. G. Ferreira and M.D. Grammatikakis, “Randomized routing on generalized hypercubes”, Theoret. Comput. Sci., Elsevier (North Holland), 158 (1-2) , pp. 53—64, 1996.
  16. M.D. Grammatikakis, (one section in) «Open problems in interconnection networks», Parallel Proc. Letters – Special Issue on Algorithmic and Structural Aspects of Interconnection Networks, eds. P. Fraigniaud, A. Liestman, D. Sotteau, World Scientific Publishing, 4 , 1993.

International Conferences

  1. George Kornaros, “Temporal Coding Schemes for Energy Efficient Data Transmission in Systems-on-Chip”, in Proceedings of IEEE Workshop on Intelligent Solutions in Embedded Systems Ancona, Italy, June 25-26, 2009. Best paper award.
  2. George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, and Helen-Catherine Leligou, «Architecture and implementation on frame aggregation unit for optical frame-based switching», International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, September 08-10, 2008, On page(s): 639-642, ISBN: 978-1-4244-1960-9, Digital Object Identifier: 10.1109/FPL.2008.4630028
  3. G.Kornaros, Th.Orphanoudakis, H-C.Leligou, «Architecture and Implementation of Traffic Shaping Integrating Networks-on-Chip and off-chip Networks», 2008 International Conference on High Performance Embedded Architectures & Compilers, 2nd Workshop on Reconfigurable Computing, Goteborg, Sweeden, January 27-29, 2008.
  4. G.Kornaros, D.Meidanis, Y. Papaefstathiou, S.Chantzandroulis, S.Blionas, «Architecture of a Consumer Lab- on-Chip for Pharmacogenomics», IEEE International Conference on Consumer Electronics (ICCE’08), Jan 11-13, 2008, Las Vegas, USA.
  5. Th.Orphanoudakis, G. Kornaros, I Mavroidis , A.Nikologiannis , I Papaefstathiou: «An Embedded Networking SoC for purely Ethernet MANs/WANs», IEEE Symposium on Computers and Communications (ISCC’07), Aveiro, Portugal, July 1-4 2007.
  6. G. Kornaros, Y. Papaefstathiou, D. Pnevmatikatos: «Dynamic Software-Assisted Monitoring of On-Chip Interconnects», DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Palais des Congrès Acropolis Nice, France, Friday April 20, 2007.
  7. Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos, “Using Buffered Crossbars for Chip Interconnection», ACM Great Lakes Symposium on VLSI (GLSVLSI2007), Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Pages: 90 – 95, Stresa-Lago Maggiore, Italy March 11 – 13, 2007.
  8. George Kornaros, Yannis Papaefstathiou: «A Buffered Crossbar-Based Chip Interconnection Architecture Supporting Quality of Service», SPL2007 – III Southern Conference on Programmable Logic, February 26-28, 2007 – Mar del Plata, Argentina, IEEE Computer Society 2007, ISBN 978-1-4244-0606-7.
  9. L. Bononi, N. Concer, M.D. Grammatikakis, M. Coppola, R. Locatelli, «NoC topologies exploration based on mapping and simulation models», in Proc. Digital Systems Design Conf. (DSD), 2006, pp. 546—549.
  10. George Kornaros, «A Buffered Cross-Bar Switch Fabric Utilizing Shared Memory», Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August – 1 September 2006, Dubrovnik, Croatia, IEEE Computer Society 2006, ISBN 0-7695-2609-8, http://doi.ieeecomputersociety.org/10.1109/DSD.2006.30
  11. Theofanis Orphanoudakis, Aristides Nikologiannis, Ioannis Papaefstathiou, George Kornaros, Iakovos Mavroidis, Nicholas Zervos, «Custom Network Processor Design for High-Performance Multiservice Access Concentrators». Proceedings of the International Conference IWSSIP 2005 (12th INTERNATIONAL WORKSHOP ON SYSTEMS, SIGNALS & IMAGE PROCESSING), 22-24 September 2005, Chalkida, Greece.
  12. Ioannis Papaefstathiou, Theofanis Orphanoudakis, Aristides Nikologiannis, George Kornaros, Iakovos Mavroidis: «Performance Evaluation of a Network Processor Based Multi-Service Access Concentrator». 12th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Gammarth, Tunisia, December 11-14th 2005.
  13. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, I. Mavroidis, Aristides Nikologiannis: «Queue Management in Network Processors». (DATE 2005: 112-117) 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. IEEE Computer Society 2005, ISBN 0-7695-2288-2.
  14. M. Coppola, S. Curaba, M.D. Grammatikakis, G. Marrucia, and F. Papariello, «OCCN: A network-on-chip modeling and simulation framework», in Proc. 7th Design Automation and Test in Europe, 2004, Paris, France, Vol. 3, pp. 174-179.
  15. Ioannis Papaefstathiou and George Kornaros, «Software Processing Performance in Network Processors», Design Automation and Test in Europe Conference (DATE’04), 2004 CNIT La Defence Paris, February 16-20, 2004.
  16. M. Coppola, S. Curaba, M.D. Grammatikakis, and G. Marrucia, «IPSIM – SystemC 3.0 enhancements for communication reï¬ﾁnement», in Proc. 6th Design Automation and Test in Europe, 2003, Munich, Germany, Vol. 2, pp. 106—111.
  17. Ioannis Papaefstathiou and George Kornaros, «Performance against cost trade-offs for Hardware Compression in 10 Gigabit Networks», 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2003), University of Sharjah, Sharjah, United Arab Emirates, December 14-17, 2003.
  18. C.Charopoulos, N.Leligou, G.Stassinopoulos, G.Kornaros, Th.Orphanoudakis, «Programmable peak-rate Gigabit shaper supporting ATM and packet-oriented traffic», International Conference on Computer, Communication and Control Technologies: CCCT ’03 and The 9th. International Conference on Information Systems Analysis and Synthesis: ISAS ‘03, July 31, August 1-2, 2003 – Orlando, Florida, USA.
  19. Th. Orphanoudakis, H.C.Leligou, George Kornaros, Ch. Charopoulos, «Accurate scheduler implementation for shaping flows of variable length packets in high-speed networking applications», Recent Advances in Communications and Computer Science, pp. 95-102, 7th WSEAS International Multiconference on Circuits, Systems, Communications and Computers (CSCC 2003) Corfu, Greece, July 7-10, 2003.
  20. George Kornaros, Th. Orphanoudakis, N. Zervos, «An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures», DSD’2003 EUROMICRO Symposium on Digital System Design, Architectures, Methods and Tools, Antalya, Turkey, September 3 – 5, 2003.
  21. George Kornaros, Ioannis Papaefstathiou, «An Innovative Resource Management Scheme for Multi-Gigabit Networking Systems», 6th IEEE International Conference on High Springer-Verlag, Estoril, peed Networks and Multimedia Communications (HSNMC’03), Portugal, July 23-25, 2003.
  22. Papaefstathiou, H.-C. Leligou, Th. Orphanoudakis, G. Kornaros, N. Zervos, G. Konstantoulakis, «An Innovative Scheduling Scheme For High Speed Network Processors», IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25 – 28, 2003.
  23. G. Kornaros, F. Orphanoudakis, I. Papaefstathiou, «Active Flow Identifiers for scalable, QoS scheduling in 10-Gbps network processors», IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25 – 28, 2003.
  24. G. Kornaros, A. Nikologiannis, I. Papaefstathiou, «A Fully-Programmable Memory Management System Supporting Queue Handling at Multi Gigabit rates», IEEE, ACM, 40th Design Automation Conference (DAC), Anaheim, California, U.S.A., June 2-6, 2003.
  25. G.Kornaros, Th. Orphanoudakis, I. Papaefstathiou, «GFS: An Efficient Implementation of Fair Scheduling for multi-Gigabit Packet Networks», IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP’03), The Hague, The Netherlands, June 24-26, 2003.
  26. Theofanis Orphanoudakis, George Kornaros, Ioannis Papaefstathiou, Helen-Catherine Leligou, Stelios Perissakis, Nick Zervos , “Scheduling components for multi-gigabit network SoCs”, SPIE’s First International Symposium on Microtechnologies for the New Millennium – VLSI Circuits and Systems (EMT102), Maspalomas, Gran Canaria (Canary Islands), Spain, 19 – 21 May 2003.
  27. K.Vlachos, T.Orphanoudakis, N.Nikolaou, G.Kornaros, K.Pramataris, S.Perissakis, J-A.Sanchez, and G. Konstantoulakis, «Processing and scheduling components in an innovative network processor architecture», Proc. of VLSI Design 2003, N.Delhi,India, January 2003.
  28. Georgios Kornaros, Dionisios Pnevmatikatos, Dimitrios Mavroidis, Panagiota Vatsolaki, Georgios Kalokerinos, Chara Xanthaki, Dimitrios Dimitriadis, Dimitrios Serpanos, and Manolis Katevenis: «On Optimizing ATLAS I, a 10Gbps ATM Switch»,7th Hellenic Conference on Informatics, August 26-29, 1999, Ioannina, Greece. Selected paper in “ADVANCES IN INFORMATICS” by Dimitrios I. Fotiadis & Stavros D. Nikolopoulos, WorldScientific Press, ISBN 981-02-4192-5, April 2000.
  29. M.D. Grammatikakis and T. Merker, «Consistency models and synchronization on Cray-T3E», in Proc. 5th SGI/Cray MPP Workshop, Bologna, Italy, 1999, pp. 248–257. Available fromhttp://www.cineca.it/mpp-workshop/proceedings.htm
  30. Dionisios Pnevmatikatos, Georgios Kornaros: «ATLAS II: Optimizing a 10Gbps Single-Chip ATM Switch», 12th Annual 1999 IEEE International ASIC/SOC Conference, September 15-18, 1999, Washington, U.S.A.
  31. M.D. Grammatikakis and S. Liesche, “Parallel priority queues on Cray-T3E”, in Proc. 4th SGI/Cray MPP Workshop, Munich, Germany, 1998, pp. 69–91. Available fromhttp://www.rzg.mpg.de/mpp-workshop/papers/ipp-report.html
  32. M.D. Grammatikakis, H. Dollani and S. Liesche, “Synchronization on Cray-T3E virtual shared memory”, in Proc. 4th SGI/Cray MPP Workshop, Munich, Germany, 1998, pp. 50–58. Available from http://www.rzg.mpg.de/mpp-workshop/papers/ipp-report.html.
  33. M.D. Grammatikakis, H. Dollani and M. Kraetzl, “Continuous multicasting on statically-allocated VC-based switches”, IEEE Conf. Global Comm. (GLOBECOM), Sydney, Australia, 1998, pp. 2387–2392.
  34. M.D. Grammatikakis, C. Eilers, M. Kraetzl, S. Liesche and T. Thielke. “Data parallel communication and sorting on CM5”, in Proc. 5th Australasian Conf. Parallel Real-Time Syst. (PART’98), Adelaide, Australia. Springer Verlag, 1998, pp. 132–140.
  35. M.D. Grammatikakis, H. Dollani and S. Liesche, “Synchronization on Cray-T3E virtual shared memory”, in Proc. 40th Cray Users Group Conf., Stuttgart, Germany, 1998.
  36. Georgios Kornaros, Panagiota Vatsolaki, Dionisios Pnevmatikatos, Chara Xanthaki, Georgios Kalokerinos, Dimitrios Serpanos, Manolis Katevenis: “Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure”, Hot Interconnects VI Symposium, August 13-15, 1998, Stanford University, Stanford, California, U.S.A.
  37. Dionisios Pnevmatikatos, Georgios Kornaros, George Kalokerinos, and Chara Xanthaki: “The Memory Structures of ATLAS I, a High Performance, 16×16 ATM Switch Supporting Backpressure”, 11th Annual 1998 IEEE International ASIC Conference, September 13-16, 1998, University of Rochester, Rochester, N.Y., U.S.A.
  38. M.D. Grammatikakis, N. Fideropoulos, F. Howell, S. Liesche, T. Thielke and A. Zachos, “Network simulation on CM5 by sorting integer con﬒ict functions”, in Proc. Parallel Comput. Conf. (PARCO), Bonn, Germany. Advances in Parallel Comput., Vol. 12, Elsevier (North Holland), 1998, pp. 459-462.
  39. M.D. Grammatikakis, N. Fideropoulos and A. Zachos, “Network simulation on Cray-T3E using MPI”, in Proc. 3rd SGI/Cray MPP Workshop, Paris, France, 1997. Available fromhttp://armoise.saclay.cea.fr/Ëœworkshop/Program.html
  40. M.D. Grammatikakis, M. Kraetzl and E. Fleury, “Shortest-path and hot-potato routing on unbuffered 2-d tori”, IEEE Conf. Global Comm. (GLOBECOM), Phoenix, AZ, 1997, pp. 165—169.
  41. M.D. Grammatikakis, M. Kraetzl and E. Fleury, “Shortest-path and hot-potato routing on unbuffered toroidal networks”, AFOSR Workshop Defense Signal Proc., Victor Harbor, South Australia, 1997 (invited paper).
  42. G. Ferreira, E. Fleury, and M.D. Grammatikakis, “Multicasting control and communications on multihop stack-ring OPS networks”, in Proc. 4th IEEE Conf. Massively Parallel Proc. using Optical Interconnections (MPPOI), Toronto, Canada, 1997, pp. 39–44.
  43. George Kornaros, Christoforos Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis: «Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control», 17th Conference on Advanced Research in VLSI, September 15-16, 1997, University of Michigan, Ann Arbor, MI, U.S.A.
  44. M.D. Grammatikakis and M. Johl, «Clock level simulations of an ATM Switch», in Proc. SCS Euro Media Conf., London, UK, 1996, pp. 149–156.
  45. M.D. Grammatikakis, «Parallel simulation of ATM switches and networks», in Proc. 2nd SGI/Cray MPP Workshop, Edinburgh, Scotland, UK, 1996. Available ashttp://www.epcc.ed.ac.uk/t3d/workshop/proceedings/Grammatikakis.ps.gz.
  46. E. Fleury, M.D. Grammatikakis, and M. Kraetzl, «Performance of STC104 vs. Telegraphos», in Proc. 7th Int. Workshop Parallel Proc. Cell Automata Arrays (PARCELLA), Berlin, Germany. Math. Research, Akademie Verlag, Vol. 96, 1996, pp. 29–37.
  47. M.D. Grammatikakis, D. F. Hsu and M. Kraetzl, «A journey into multicomputer routing algorithms», Keynote Paper, in Proc. 1st IEEE Symp. Parallel Alg. Arc h. Synth. (PAS), Aizu, Japan, 1995, pp. 19–27. Keynote paper for PAS Conference.
  48. M.D. Grammatikakis and M. Kraetzl, «Probabilistic models of network routers», in Proc. Parallel Computer Conf. (PARCO), Ghent, Belgium. Advances in Parallel Comput., Vol. 11, Elsevier (North-Holland), 1995, pp. 613–616.
  49. M.D. Grammatikakis and M. Kraetzl, «Simulations of crossbar switches for parallel systems», in Proc. SCS Eur. Sim. Conf. (EUROSIM), Vienna, Austria, 1995, pp. 535–540.
  50. P. Vatsolaki, G. Kalokerinos, M. Stratakis , Ch. Xanthaki, M. Ligerakis, G. Kornaros, A. Dollas, G. Papadourakis, M. Katevenis: «The Implementation of Telegraphos: a High Speed Communication Architecture», In Proceedings of the 5th Panhellenic Informatics Conference Athens Greece, December 1995.
  51. M.D. Grammatikakis, J. S. Jwo, M. Kraetzl and Suh-Hui Wang, «Dynamic and static packet routing on symmetric communication networks», in Proc. IEEE Conf. Global Comm. (GLOBECOM), San Francisco, CA, 1994, pp. 1571—1575.
  52. G. Ferreira and M.D. Grammatikakis, «Improved probabilistic routing on generalized hypercubes», in Proc. Parallel Arch. Lang. Europe (PARLE), Athens, Greece. Lecture Notes in Computer Science, Springer Verlag, Vol. 817, 1994, pp. 1–12.
  53. M.D. Grammatikakis, J. S. Jwo and M. Kraetzl, «Simulator of router performance on MIMD topologies», in Proc. SCS Eur. Sim. Symp. (ESS), Istanbul, Turkey, 1994, Vol. 3, pp. 88–90.
  54. M.D. Grammatikakis, D. F. Hsu and F. K. Hwang, «Adaptive and oblivious routing on the d-cube», in Proc. 4th ACM Int. Symp. Symb. Algebraic Comput. (ISAAC), Hong-Kong. Lecture Notes in Computer Science, Springer Verlag, Vol. 762, 1993, pp. 167—175.
  55. M.D. Grammatikakis, J. S. Jwo and A. Damianakis, «Simulating communication in parallel computer systems», in Proc. SCS Eur. Sim. Symp. (ESS), Delft, The Netherlands, 1993, pp. 477–482.
  56. M.D. Grammatikakis, D. F. Hsu and F. K. Hwang, «Universality of d-cube, d < 8», in Proc. Parallel Computer Conf. (PARCO), Grenoble, France. Adv. in Parallel Comput., Elsevier (North Holland), Vol. 9, 1993, pp. 517—520.
  57. M.D. Grammatikakis and J. S. Jwo, «Simulating store-forward communication», in Proc. Parallel Computer Conf. (PARCO), Grenoble, France. Advances in Parallel Comput., Elsevier (North Holland), Vol. 9, 1993, pp. 681–684.
  58. M.D. Grammatikakis and J. S. Jwo, «Greedy permutation routing on cayley graphs», in Proc. 2nd Joint Int. Conf. Vector and Parallel Proc. (CONPAR), Lyon, France. Lecture Notes in Computer Science, Springer Verlag, Vol. 634, 1992, pp. 839–840.
  59. M.D. Grammatikakis and J. S. Jwo, «A discrete-event simulator of communication algorithms in interconnection networks», in Proc. 9th Symp. Theor. Aspects Comput. Sci. (STACS), Paris, France. Lecture Notes in Computer Science, Springer Verlag, Vol. 577, 1992, pp. 609–610.
  60. M.D. Grammatikakis, «Probabilistic routing algorithms for generalized hypercubes», in Proc. 25th Conf. Inf. Sci. Syst. (CISS), Baltimore, MD, 1991, pp. 125—131.
  61. M.D. Grammatikakis, «Probabilistic routing in distributed architectures», in Proc. 5th SIAM Conf. Parallel Proc., Houston, TX, 1991, (abstract).
  62. M.D. Grammatikakis, S. Lakshmivarahan and S. K. Dhall, «Packet routing for generalized hypercube», in Proc. 24th Conf. Inf. Sci. Syst. (CISS), Princeton, NJ, 1990, pp. 159-164.
  63. M.D. Grammatikakis, S. Lakshmivarahan and S. K. Dhall, «Experiments on probabilistic routing for a generalized hypercube», in Proc. 3rd Symp. Applied Comput. (SAC), Stillwater, OK, 1989, pp. 131 – 133.